The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same; and, in particular, the invention relates to a technology applicable to a semiconductor integrated circuit device having a DRAM (dynamic random access memory).
A memory cell in a DRAM is arranged at each of the points of intersection of a plurality of word lines and a plurality of bit lines, which are arranged in the form of a matrix on the main surface of a semiconductor substrate, and the memory cell is constituted by one MISFET (metal insulator semiconductor field effect transistor) for selecting the memory cell and one capacitance element (capacitor) for storing information connected in series thereto.
The above-mentioned MISFET for selecting a memory cell is constituted mainly by a gate oxide film, a gate electrode integrally formed with the word line, and a pair of semiconductor regions which constitute a source and a drain. The capacitance element for storing information is arranged on top of the MISFET for selecting a memory cell and is electrically connected to one of the pair of source and drain. Also, the bit line is arranged on top of the MISFET for selecting a memory cell and is electrically connected to the other of the pair of source and drain.
The above-mentioned DRAM having a capacitance element for storing information on top of a MISFET for selecting a memory cell, that is, having a so-called stacked capacitor structure, adopts either a capacitor-over-bit line (COB) structure in which the capacitance element for storing information is arranged over a bit line or a capacitor-under-bit line (CUB) structure in which the capacitance element for storing information is arranged under the bit line, and the former structure (COB structure) is more suitable for making a finely patterned memory cell. This is because, in order to increase the amount of stored charges of the finely patterned capacitance element for storing information, the capacitance element for storing information is required to have a three-dimensional structure to increase its surface area; and, in the case of the CUB structure in which the bit line is arranged over the capacitance element for storing information, the aspect ratio of a contact hole for connecting the bit line to the MISFET for selecting the memory cell is made extremely large, and, hence, it is difficult to form the contact hole.
In a DRAM having the COB structure in which the capacitance element for storing information is arranged on the bit line, the bit line is arranged on the MISFET for selecting a memory cell via a silicon oxide film (a first silicon oxide film) and the capacitance element for storing information is arranged on the bit line via a silicon oxide film (a second silicon oxide film). And, one of the pair of source and drain of the MISFET for selecting a memory cell is connected to the bit line through a contact hole formed in the first silicon oxide film and the other of the pair of source and drain of the MISFET for selecting a memory cell is connected to the capacitance element for storing information through a hole formed in the second silicon oxide film through between the gap neighboring bit lines and through a contact hole formed in the first silicon oxide film underlying the through hole formed in the second silicon oxide film.
Accordingly, if the pitch of the bit line is reduced in a DRAM having the COB structure to reduce the size of a memory cell, it is difficult to ensure an alignment allowance between the bit line and the through hole passing the gap between the bit lines, which in turn will present a problem in that a plug buried in the through hole and the bit line may create a short circuit.
As a countermeasure to avoid the drawback described above, it is possible to adopt the so-called self-alignment contact (SAC) technology that the top and the side wall of the bit line is covered with a silicon nitride film and a through hole is made in a self-alignment manner with respect to the bit line by using a difference in etching rate between the silicon nitride film and the second silicon oxide film of the region where the through hole is made.
However, in the case where the self-alignment contact (SAC) technology is adopted in which the surrounding area of the bit line is covered with the silicon nitride film, the dielectric constant of silicon nitride is more than two times that of silicon oxide and hence increases the parasitic capacitance of the bit line, which in turn presents another problem in that it becomes difficult to detect a signal stored in the capacitance element for storing information.
As a second countermeasure to ensure an alignment allowance between the bit line and the through hole, it is possible to adopt a method in which the width of a photoresist film used for patterning a metal film for the bit line is made fine to make the width of the bit line fine. In order to make the width of the photoresist film fine, the photoresist film applied on top of the metal film for the bit line is exposed to light and developed to form a photoresist film having a width determined by the minimum size of the limit of resolution of the photolithography, and then the photoresist film is anisotropically etched to further narrow the width thereof.
However, the above-mentioned method of making the width of the photoresist film fine by etching it in an anisotropic manner presents some difficulty in controlling the amount of etching of the photoresist film with high accuracy, and hence it presents a problem in that the stability in size of the photoresist film is reduced after it is etched. Also, in the case where the metal film is patterned by using the photoresist film having a width finer than the minimum width determined by the limit of resolution of the photolithography, another problem is also presented in that a variation in the amount of etching of the photoresist film increases and the stability in size of the bit line is reduced.
Further, in the case where the photoresist film applied on top of the metal film is finely patterned, still another problem is presented in that a variation in the size of the photoresist caused by halation or the like becomes apparent. Also, when a reflection preventing film or the like is formed on the film underlying the photoresist film as a countermeasure against this problem, a further problem is presented in that the controllability of etching is reduced.
Also, in the manufacturing process of the DRAM having the above-mentioned COB structure, in order to form the capacitance element for storing information on top of the bit line with good yield, it is necessary to deposit a silicon oxide film (a second silicon oxide film) in the gap between the bit lines and on top of the bit line and then to planarize the surface of the silicon oxide film using a CMP method. For this reason, in order to ensure a polishing margin, it is necessary to leave the silicon oxide film to some extent of thickness on top of the bit line, which results in an increase the level of the region where the memory cell is formed (memory array). As a result, this increases the aspect ratio of a connection hole for connecting an Al wiring formed on top of the capacitance element for storing information to the MISFET of the peripheral circuit and hence reduces the manufacturing yield of the connection hole and the reliability in connection of a conductive layer buried in the connection hole.
It is an object of the present invention to provide a technology for reducing the size of a memory cell of a DRAM by making the width of a bit line finer than the minimum size determined by the limit of resolution of photolithography.
It is another object of the present invention to provide a technology for improving the detection sensitivity of a signal stored in a capacitance for storing information by reducing the capacitance parasitic on the bit line.
It is still another object of the present invention to provide a technology for improving the manufacturing yield of a DRAM by reducing the height of a memory array.
The above-mentioned objects and other objects and new features will become apparent from the description of the present specification and its accompanying drawings.
Of the features disclosed in the present specification, typical aspects thereof will be outlined in brief in the following.
(1) A semiconductor integrated circuit device in accordance with the present invention has, on the main surface of a semiconductor substrate, a memory cell including a MISFET for selecting a memory cell which is provided with a gate electrode integrally formed with a word line extending in a first direction, a wiring trench which is formed in an insulating film formed over the MISFET for selecting a memory cell and which extends in a second direction intersecting the first direction, a bit line formed in the wiring trench and electrically connected to one of a pair of source and drain of the NISFET for selecting the memory cell, and a capacitance element for storing information formed over the bit line and electrically connected to the other of the pair of source and drain, wherein a second insulating film is formed over the inside wall of the wiring trench and wherein the bit line is formed inside the second insulating film.
(2) A semiconductor integrated circuit device in accordance with the present invention has, in the above-mentioned aspect 1, the width of the bit line smaller than the interval between the neighboring bit lines.
(3) A semiconductor integrated circuit device in accordance with the present invention has, in the above-mentioned aspect 1, has a part of the bit line buried in a first contact hole formed in the insulating film at the bottom of the wiring trench and directly connected to one of the pair of source and drain.
(4) A semiconductor integrated circuit device in accordance with the present invention has, in the above-mentioned in aspect 1, the bit line electrically connected to one of the pair of source and drain via a plug buried in a first contact hole formed in the insulating film at the bottom of the wiring trench.
(5) A semiconductor integrated circuit device in accordance with the present invention has, in the above-mentioned aspect 3 or aspect 4, the first contact hole which is constituted by a plan pattern having a diameter larger in the first direction than in the second direction and a part of which extends over an active region where the MISFET for selecting a memory cell is formed and the other part of which extends over a device isolating region directly below the bit line.
(6) A semiconductor integrated circuit device in accordance with the present invention has, in the above-mentioned aspect 1, an active region where the MISFET for selecting a memory cell is formed and which is constituted by a plan pattern extending slenderly along the second direction and having a portion projecting in the first direction at the one side of the center thereof.
(7) A semiconductor integrated circuit device in accordance with the present invention has, in the above-mentioned aspect 1, the surface of the bit line which is flush with the surface of the insulating film.
(8) A method of manufacturing a semiconductor integrated circuit device in accordance with the present invention includes the following steps:
(A) forming on the main surface of a semiconductor substrate a MISFET for selecting a memory cell which is provided with a gate electrode integrally formed with a word line extending in a first direction and then forming a first insulating film on the top of the MISFET for selecting a memory cell;
(B) etching the first insulating film to form a second contact hole extending to the other of a pair of source and drain of the NISFET for selecting a memory cell and then forming a plug in the second contact hole;
(c) forming on the top of the first insulating film a third insulating film which is different in an etching rate from the first insulating film and then forming on the top of the third insulating film a fourth insulating film which is different in an etching rate from the third insulating film;
(d) etching the fourth insulating film by using the third insulating film as an etching stopper to form a wiring trench extending in a second direction intersecting the first direction;
(e) forming a second insulating film having a thickness smaller than half the width of the wiring trench on the fourth insulating film including the inside of the wiring trench;
(f) sequentially etching the second insulating film inside the wiring trench, the third insulating film below it, and the first insulating film to form a first contact hole extending to one of the pair of source and drain of the MISFET for selecting a memory cell; and
(g) depositing a first conductive film to be the material of a bit line on the second insulating film including the inside of the first contact hole and then polishing the first conductive film and the second insulating film on the fourth insulating film respectively by a chemical mechanical polishing method to form a bit line in each of the wiring trench and the first contact hole.
(9) A method of manufacturing a semiconductor integrated circuit device in accordance with the present invention includes the following steps:
(A) forming on the main surface of a semiconductor substrate a MISFET for selecting a memory cell which is provided with a gate electrode integrally formed with a word line extending in a first direction and then forming a first insulating film on the top of the MISFET for selecting a memory cell;
(B) etching the first insulating film to form a first contact hole extending to one of a pair of source and drain of the MISFET for selecting a memory cell and a second contact hole extending to the other of the pair of source and drain and then forming a plug in each of the first and second contact holes;
(c) forming on the top of the first insulating film a third insulating film which is different in an etching rate from the first insulating film and then forming on the top of the third insulating film a fourth insulating film which is different in an etching rate from the third insulating film;
(d) etching the fourth insulating film by using the third insulating film as an etching stopper to form a wiring trench extending in a second direction intersecting the first direction;
(e) forming a second insulating film on the fourth insulating film including the inside of the wiring trench and then anisotropically etching the second insulating film to form a side wall spacer on the side wall of the wiring trench;
(f) etching the third insulating film in the wiring trench and the first insulating film below the third insulating film to form a first through hole extending to the first contact hole; and
(g) depositing a first conductive film to be the material of a bit line on the fourth insulating film including the inside of the first through hole and then polishing the first conductive film by a chemical mechanical polishing method to form a bit line in each of the wiring trench and the first through hole.
(10) A method of manufacturing a semiconductor integrated circuit device in accordance with the present invention is a method in which, in the above-mentioned aspect 8 or aspect 9, the width of a gate electrode integrally formed with the word line and the interval between the gate electrodes are formed in the minimum size determined by the limit of resolution of a photolithography and in which the width of the wiring trench and the interval between the wiring trenches are formed in the minimum size determined by the limit of resolution of the photolithography.
(11) A method of manufacturing a semiconductor integrated circuit device in accordance with the present invention is a method in which, in above-mentioned aspect 8, after the first contact hole extending to one of the pair of source and drain of the MISFET for selecting a memory cell is formed in the step (f), impurity ions of the same conductive type as is used in the pair of source and drain are implanted into one of the pair of source and drain through the first contact hole.
(12) A method of manufacturing a semiconductor integrated circuit device in accordance with the present invention is a method in which, in above-mentioned aspect 8 or aspect 9, after a metal film having a high melting point and to be the material of a bit line is deposited in the first through hole in the step (g), the substrate is annealed to form a silicide layer at the interface between the metal film having a high melting point and the substrate.
(13) A method of manufacturing a semiconductor integrated circuit device in accordance with the present invention further includes the following steps in above-mentioned aspect 8 or aspect 9:
(h) forming a fifth insulating film on the top of the fourth insulating film and then sequentially etching the fifth insulating film, the fourth insulating film underlying the fifth insulating film, the third insulating film, and the first insulating film to form a second through hole extending to the second contact hole;
(i) forming a plug in the second through hole and then forming on the top of the fifth insulating film a sixth insulating film which is different in an etching rate from the fifth insulating film and then forming a seventh insulating film on the top of the sixth insulating film and then forming a trench in the seventh insulating film and the sixth insulating film underlying the seventh insulating film; and
(j) forming a capacitance element for storing information in the trench and then electrically connecting the capacitance element for storing information to the other of the pair of source and drain of the MISFET for selecting a memory cell through the second through hole and the second contact hole below the second through hole.
14. A method of manufacturing a semiconductor integrated circuit device in accordance with the present invention is a method in which in the above-mentioned aspect 13, the fifth insulating film and the fourth insulating film are etched away by using the third insulating film as an etching stopper.
15. A method of manufacturing a semiconductor integrated circuit device in accordance with the present invention further includes the following steps in the above-mentioned aspect 13:
(k) forming the MISFET of a peripheral circuit in the step (A);
(l) forming the first layer wiring of a peripheral circuit in the step (g); and
(m) forming an eighth insulating film on the top of the capacitance element for storing information after forming the capacitance element for storing information in the step (j) and then sequentially etching the eighth insulating film, the seventh insulating film, the sixth insulating film, and the fifth insulating film to form a through hole extending to the first layer wiring of the peripheral circuit.
(16) A method of manufacturing a semiconductor integrated circuit device in accordance with the present invention is a method in which, in the above-mentioned aspect 15, the eighth insulating film and the seventh insulating film are etched away by using the sixth insulating film as an etching stopper.